Lightnews — Scholar-powered news

LightNews

arXiv cs.AR Hardware Architecture

@csar-bot.bsky.social

21 followers 1 following 3.1K posts

Unofficial bot by @vele.bsky.social w/ http://github.com/so-okada/bXiv https://arxiv.org/list/cs.AR/new List https://bsky.app/profile/vele.bsky.social/lists/3lim7ccweqo2j ModList https://bsky.app/profile/vele.bsky.social/lists/3lim3qnexsw2g

Posts Media Videos Starter Packs

arXiv cs.AR Hardware Architecture @csar-bot.bsky.social · 3h

Hengrui Zhang, Pratyush Patel, August Ning, David Wentzlaff: SPAD: Specialized Prefill and Decode Hardware for Disaggregated LLM Inference https://arxiv.org/abs/2510.08544 https://arxiv.org/pdf/2510.08544 https://arxiv.org/html/2510.08544

arXiv cs.AR Hardware Architecture @csar-bot.bsky.social · 3h

Qingxiu Liu, Jiazhen Cai, Siyuan Sheng, Yuhui Chen, Lu Tang, Zhirong Shen, Patrick P. C. Lee: FMCache: File-System Metadata Caching in Programmable Switches https://arxiv.org/abs/2510.08351 https://arxiv.org/pdf/2510.08351 https://arxiv.org/html/2510.08351

arXiv cs.AR Hardware Architecture @csar-bot.bsky.social · 3h

Anastasios Petropoulos, Theodore Antonakopoulos: A Scalable FPGA Architecture With Adaptive Memory Utilization for GEMM-Based Operations https://arxiv.org/abs/2510.08137 https://arxiv.org/pdf/2510.08137 https://arxiv.org/html/2510.08137

arXiv cs.AR Hardware Architecture @csar-bot.bsky.social · 3h

Parker Hao Tian, Zahra Yousefijamarani, Alaa Alameldeen: DL-PIM: Improving Data Locality in Processing-in-Memory Systems https://arxiv.org/abs/2510.07719 https://arxiv.org/pdf/2510.07719 https://arxiv.org/html/2510.07719

arXiv cs.AR Hardware Architecture @csar-bot.bsky.social · 3h

Georgia Antoniou, Haris Volos, Jawad Haj Yahya, Yiannakis Sazeides: How long can you sleep? Idle Time System Inefficiencies and Opportunities https://arxiv.org/abs/2510.07449 https://arxiv.org/pdf/2510.07449 https://arxiv.org/html/2510.07449

arXiv cs.AR Hardware Architecture @csar-bot.bsky.social · 3h

[2025-10-10 Fri (UTC), 5 new articles found for csAR Hardware Architecture]

Reposted by arXiv cs.AR Hardware Architecture

arXiv cs.ET Emerging Technologies @cset-bot.bsky.social · 1d

Mateos Serrano, et al.: From Neural Sensing to Stimulation: An Interdisciplinary Roadmap for Neurotechnology https://arxiv.org/abs/2510.07116 https://arxiv.org/pdf/2510.07116 https://arxiv.org/html/2510.07116

Reposted by arXiv cs.AR Hardware Architecture

arXiv cs.DC Distributed, Parallel, and Cluster Computing @csdc-bot.bsky.social · 1d

Martin Wilhelm, Franz Freitag, Max Tzschoppe, Thilo Pionteck: Evaluating Rapid Makespan Predictions for Heterogeneous Systems with Programmable Logic https://arxiv.org/abs/2510.06998 https://arxiv.org/pdf/2510.06998 https://arxiv.org/html/2510.06998

arXiv cs.AR Hardware Architecture @csar-bot.bsky.social · 1d

Kim, Gu, Baek, Lo, Min, Shin, Kim, Park, Maeng: Cocoon: A System Architecture for Differentially Private Training with Correlated Noises https://arxiv.org/abs/2510.07304 https://arxiv.org/pdf/2510.07304 https://arxiv.org/html/2510.07304

arXiv cs.AR Hardware Architecture @csar-bot.bsky.social · 1d

Bindu G Gowda, Yogesh Goyal, Yash Gupta, Madhav Rao: Hardware-Efficient CNNs: Interleaved Approximate FP32 Multipliers for Kernel Computation https://arxiv.org/abs/2510.06767 https://arxiv.org/pdf/2510.06767 https://arxiv.org/html/2510.06767

arXiv cs.AR Hardware Architecture @csar-bot.bsky.social · 1d

Li, Qin, Peng, Wan, Qu, Han, Zheng, Zhang, , , Chen, , : RTGS: Real-Time 3D Gaussian Splatting SLAM via Multi-Level Redundancy Reduction https://arxiv.org/abs/2510.06644 https://arxiv.org/pdf/2510.06644 https://arxiv.org/html/2510.06644

arXiv cs.AR Hardware Architecture @csar-bot.bsky.social · 1d

Debendra Das Sharma, Swadesh Choudhary, Peter Onufryk, Rob Pelt: On-Package Memory with Universal Chiplet Interconnect Express (UCIe): A Low Power, High Bandwidth, Low Latency and Low Cost Ap... https://arxiv.org/abs/2510.06513 https://arxiv.org/pdf/2510.06513 https://arxiv.org/html/2510.06513

arXiv cs.AR Hardware Architecture @csar-bot.bsky.social · 1d

[2025-10-09 Thu (UTC), 4 new articles found for csAR Hardware Architecture]

Reposted by arXiv cs.AR Hardware Architecture

arXiv cs.DC Distributed, Parallel, and Cluster Computing @csdc-bot.bsky.social · 2d

Zhongkai Yu, Yue Guan, Zihao Yu, Chenyang Zhou, Shuyi Pei, Yangwook Kang, Yufei Ding, Po-An Tsai: Orders in Chaos: Enhancing Large-Scale MoE LLM Serving with Data Movement Forecasting https://arxiv.org/abs/2510.05497 https://arxiv.org/pdf/2510.05497 https://arxiv.org/html/2510.05497

Reposted by arXiv cs.AR Hardware Architecture

arXiv cs.DC Distributed, Parallel, and Cluster Computing @csdc-bot.bsky.social · 2d

Xi Wang, Bin Ma, Jongryool Kim, Byungil Koh, Hoshik Kim, Dong Li: cMPI: Using CXL Memory Sharing for MPI One-Sided and Two-Sided Inter-Node Communications https://arxiv.org/abs/2510.05476 https://arxiv.org/pdf/2510.05476 https://arxiv.org/html/2510.05476

arXiv cs.AR Hardware Architecture @csar-bot.bsky.social · 2d

Panagiota Nikolaou, Freddy Gabbay, Jawad Haj-Yahya, Yiannakis Sazeides: An opportunity to improve Data Center Efficiency: Optimizing the Server's Upgrade Cycle https://arxiv.org/abs/2510.05787 https://arxiv.org/pdf/2510.05787 https://arxiv.org/html/2510.05787

arXiv cs.AR Hardware Architecture @csar-bot.bsky.social · 2d

Tianhao Zhu, Dahu Feng, Erhu Feng, Yubin Xia: From Principles to Practice: A Systematic Study of LLM Serving on Multi-core NPUs https://arxiv.org/abs/2510.05632 https://arxiv.org/pdf/2510.05632 https://arxiv.org/html/2510.05632

arXiv cs.AR Hardware Architecture @csar-bot.bsky.social · 2d

Ibnat, Calzada, Ihtemam, Saha, Zhou, Farahmandi, Tehranipoor: DeepV: A Model-Agnostic Retrieval-Augmented Framework for Verilog Code Generation with a High-Quality Knowledge Base https://arxiv.org/abs/2510.05327 https://arxiv.org/pdf/2510.05327 https://arxiv.org/html/2510.05327

arXiv cs.AR Hardware Architecture @csar-bot.bsky.social · 2d

Pan, Xia, Hsu, Hu, Kim, Sharda, Zhou, Kim, Yu, Rosing, Kang: Stratum: System-Hardware Co-Design with Tiered Monolithic 3D-Stackable DRAM for Efficient MoE Serving https://arxiv.org/abs/2510.05245 https://arxiv.org/pdf/2510.05245 https://arxiv.org/html/2510.05245

arXiv cs.AR Hardware Architecture @csar-bot.bsky.social · 2d

[2025-10-08 Wed (UTC), 4 new articles found for csAR Hardware Architecture]

Reposted by arXiv cs.AR Hardware Architecture

arXiv cs.PL Programming Languages @cspl-bot.bsky.social · 3d

Shihan Fang, Wenxin Zheng: Retrofitting Control Flow Graphs in LLVM IR for Auto Vectorization https://arxiv.org/abs/2510.04890 https://arxiv.org/pdf/2510.04890 https://arxiv.org/html/2510.04890

arXiv cs.AR Hardware Architecture @csar-bot.bsky.social · 3d

Emad Jacob Maroun: A Dense and Efficient Instruction Set Architecture Encoding https://arxiv.org/abs/2510.04158 https://arxiv.org/pdf/2510.04158 https://arxiv.org/html/2510.04158

arXiv cs.AR Hardware Architecture @csar-bot.bsky.social · 3d

[2025-10-07 Tue (UTC), 1 new article found for csAR Hardware Architecture]

Reposted by arXiv cs.AR Hardware Architecture

arXiv cs.LG Machine Learning @cslg-bot.bsky.social · 4d

Jindan Li, Zhaoxian Wu, Gaowen Liu, Tayfun Gokmen, Tianyi Chen: In-memory Training on Analog Devices with Limited Conductance States via Multi-tile Residual Learning https://arxiv.org/abs/2510.02516 https://arxiv.org/pdf/2510.02516 https://arxiv.org/html/2510.02516

Reposted by arXiv cs.AR Hardware Architecture

arXiv cs.CR Cryptography and Security @cscr-bot.bsky.social · 4d

Weihang Li, Pete Crowley, Arya Tschand, Yu Wang, Miroslav Pajic, Daniel Sorin: Rigorous Evaluation of Microarchitectural Side-Channels with Statistical Model Checking https://arxiv.org/abs/2510.02475 https://arxiv.org/pdf/2510.02475 https://arxiv.org/html/2510.02475