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instlatx64.bsky.social
InstLatX64
@instlatx64.bsky.social
270 followers 0 following 320 posts
x86/x64, SIMD, #AVX512, "Aha!" moments.
I have been writing code since 1986.

Budapest, Europe
https://instlatx64.github.io/InstLatx64/
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instlatx64.bsky.social
#Intel released the "Intel #Xeon6 vs #AMD #EPYC Competitive Infographic" pdf:
cdrdv2-public.intel.com/859022/intel...
December 7, 2025 at 7:27 PM
instlatx64.bsky.social
#Intel released the "Trust Domain Extensions (Intel TDX) Module Extension for Pre-Migration" 869278 001US pdf:
cdrdv2-public.intel.com/869278/TDX%2...
November 28, 2025 at 8:55 AM
instlatx64.bsky.social
#AMD released the "PQOS White Paper for AMD #EPYC 9004 and 9005 Series Processors" 69127 1.00 pdf
docs.amd.com/v/u/en-US/69...
November 27, 2025 at 12:45 PM
instlatx64.bsky.social
#Intel released the "Intel Architecture Memory Protections for Confidential Computing" Technical Paper 869103 pdf
www.intel.com/content/www/...
November 27, 2025 at 8:48 AM
instlatx64.bsky.social
#AMD "Beyond Cloud First: The Rise of Hybrid Consistency" pdf:
www.amd.com/content/dam/...
November 26, 2025 at 10:47 AM
instlatx64.bsky.social
It seems, #AMD utilizes their #Zen5 #FireRange CPUs in the embedded server space too:
#EPYC9005 - #SP5
#EPYC8005 - #SP6
#EPYC4005 - #AM5
#EPYC2005 - #FL1

docs.amd.com/v/u/en-US/ug...
November 25, 2025 at 9:11 AM
instlatx64.bsky.social
If the CCD of #Zen6 #Threadripper is
- classic, like in #Zen4 and #Zen5, then the maximum number of cores is only 4x12=48;
- dense, then the number of cores can be 128, but with a frequency limit, like in #Zen4c (~3.1 GHz) and #Zen5c (~3.7 GHz);
November 24, 2025 at 3:12 PM
instlatx64.bsky.social
I think the "more AI pipelines" on #AMD #Zen6 means that ADD/SUB/MIN/MAX/CVT uops of "New AI Datatype"(=FP16) can go into FP23 ports also, against the FP01-bounded #AVX512_VNNI / #AVX_VNNI uops.
November 20, 2025 at 12:11 PM
instlatx64.bsky.social
The problem with #AMD #Zen6 #Threadripper is that the components revealed so far (12-core classic, 32-core dense, 4 CCD/IO chips) cannot be used to build a 96-core, frequency-optimized version in the size of #SP8 socket, which could replace the current top-SKU 9995WX.
November 20, 2025 at 8:47 AM
instlatx64.bsky.social
The #Zen6-based #AMD #Threadripper is missing from this chart. I don't recall seeing its codename, does it even exist?
November 17, 2025 at 9:40 AM
instlatx64.bsky.social
#AMD refreshed the "Revision Guide for AMD Family 19h Models 10h-1Fh Processors" 57095 to v1.05 pdf
( #Genova #Zen4 B0 CPUID A10F11 #EPYC )
docs.amd.com/v/u/en-US/57...
November 14, 2025 at 2:15 PM
instlatx64.bsky.social
#AMD refreshed the "Revision Guide for AMD Family 19h Models A0h-AFh Processors" 57926 to v1.05 pdf
( #Bergamo #Zen4c A0 CPUID AA0F02 #EPYC )
docs.amd.com/v/u/en-US/57...
November 14, 2025 at 2:15 PM
instlatx64.bsky.social
#Intel released the 60th edition of the ISA Extensions Reference with official announcement of #AVX10 and #APX support on #NovaLake, and FP8 type clarifications.
Download:
cdrdv2-public.intel.com/869288/31943...
#DiamondRapids #NovaLake #WildcatLake #PantherCove #CoyoteCove #ArcticWolf
November 13, 2025 at 8:07 AM
instlatx64.bsky.social
Today I learned: At least 3 #AVX512 levels were planned, but they never released:
#AVX512QVNNI - byte form of 4VNNIW, it would extinct with KNM/MIC;
#AVX512DFMA - VDF[,n]MADD[P,S][S,D] - I have no idea what the difference between FMA & DFMA;
#AVX512BITALG2 - this is the most interesting for me;
1/3
November 11, 2025 at 1:39 PM
instlatx64.bsky.social
The current VNNI landscape
#AMD #Intel #Zen6 #AVX10_2 #AVX_VNNI #AVX_VNNI_INT8 #AVX_VNNI_INT16 #DiamondRapids #NovaLake
November 9, 2025 at 8:44 PM
instlatx64.bsky.social
Visualised AMD-SB-7055 issue on a #Zen5 #AMD #Ryzen 9 9950X. The zeroed #RDSEED rate can exceed the 3% under concurrent execution...
www.amd.com/en/resources...
November 7, 2025 at 10:38 AM
instlatx64.bsky.social
#Intel refreshed the "Intel Virtualization Technology for Directed I/O Architecture Specification" pdf to 5.1
cdrdv2-public.intel.com/868911/D5139...
November 7, 2025 at 9:21 AM
instlatx64.bsky.social
#Intel released the 89th edition of the Software Developer’s Manuals with a new SEAM, and completely rewritten CPUID (with domain info) section:
All-in-One:
cdrdv2-public.intel.com/868137/32546...
Changes v81:
cdrdv2-public.intel.com/868136/25204...
UDB (opcode D6h) canonized
October 29, 2025 at 9:51 AM
instlatx64.bsky.social
Not a clear commitment, but a very good sign: #APX appeared in Mark Papermaster's presentation
#OCP2025 #AMD #x86EAG
www.amd.com/en/blogs/202...
youtu.be/Z36PjXFBmig?...
October 27, 2025 at 11:36 AM
instlatx64.bsky.social
Unfortunately, #Intel does not answer openly Game.Keeps.Loading 's question regarding #NovaLake ISA:
community.intel.com/t5/Mobile-and-Desktop-Processors/Intel-APX-ACX-10-2/m-p/1723564#M86387

#APX #AVX10_1 #AVX10_2 #AVX512
October 27, 2025 at 9:21 AM
instlatx64.bsky.social
#Intel #VPMM is back in the 7th edition of "Intel® TDX Module Base Architecture Specification (What Changed)".
Probably just a documentation bug.
cdrdv2-public.intel.com/867556/intel...
October 22, 2025 at 12:21 PM
instlatx64.bsky.social
#Intel #PantherLake presentation:
www.intel.com/content/www/...
#CougarCove #Darkmont #Intel18A
October 16, 2025 at 2:50 PM
instlatx64.bsky.social
#AMD & #Intel unified future instructions:
#FRED #AVX10 #ChkTag #ACE (=ACE (Advanced Matrix Extensions for Matrix Multiplication): www.amd.com/en/blogs/202...
October 14, 2025 at 7:17 AM
instlatx64.bsky.social
The Netwide Assembler 3.01 is ready and supports the full #DiamondRapids and #NovaLake instruction sets:
nasm.us
#AVX10_2 #AVX10_VNNI_INT #APX #AMX_FP8 #AMX_TF32 #AMX_COMPLEX #AMX_AVX512 #AMX_MOVRS
October 11, 2025 at 10:07 AM
instlatx64.bsky.social
#Intel #ClearwaterForest #Xeon6+ presentation:
cdrdv2-public.intel.com/866623/xeon-...
#Darkmont #Intel18A #LGA7529
October 10, 2025 at 9:29 PM