Currently on it! I am currently deep into the vertex shader, writing the routines to transform the vertics in assembler. Object format and how the drawing pipeline is formated are already done! And welcome on the hardware train! Here you will see how software and hardware work together in "harmony"

I packed it full with a lot of new stuff i had to develop over time like the half precision FPU and the MMU. It also comes with 4-stage partial forwarding pipeline, interrupts with different priorities, timer, ring mode, a lot of MMU configurations, separate main memory/IO address space, ...

As a german bread enjoyer i can confirm: perfection

Btw. the ROB is messy but works quite well. But you can see here why implicit renaming designs weren't much of a thing and why explicit renaming is the name of the games today

Okay, a little more spoiling: i am creating an universal compiler which you can feed a simple .json with your ISAs instruction and behaviour and then does the rest without much intervention. That is why i am going this route. But fair, i could at that point prob even use something like LLVM

Ah okay, i understood. Well that was the initial idea: start with the current universal assembler and then putting the compiler on top. But i am derivating here since i need a custom IR for some suprise that will help us later. Can't spoil too much rn since it is still all just could/should/hope

Ah thank you! Well, i got an assembler running but there is quite a lot more to the story since the compiler will be also a technological demonstrator for something that looks quite promising (for short: universal compiler). But any help is welcome and i will definitely make a deep dive into yours!

Thanks for the double reminder...