It is not uncommon to see abort points during LEC. They are the key points that have not been proven either equivalent or non-equivalent based on the current tool settings, such as compare effort or compare algorithms. There are several possible causes of abort points: Don’t Care conditions, such as out-of-range index and X-assignments. They can increase complexity for comparison.

During test case development, the trial and error process often causes re-compilation and re-elaboration of the entire database, including testbench (TB), DUT, C-model, and sometimes even UPF if it is for power-aware verification. When the database is large, rebuilding everything is time consuming. There are several ways to optimize re-build time during test case development. Split Compilation on TB and DUT…

I. The Imperative of Testing: Quality, Cost, and Reliability Semiconductor testing is a non-negotiable step in modern manufacturing, driven by quality, reliability, and cost control. The key tool is the Automatic Test Equipment (ATE), a sophisticated, computer-controlled machine that runs software to apply electrical signals and verify a chip's performance. The Necessity of Testing Testing is a delicate economic trade-off between maximizing production…

Posts about cache-coherent written by chipressian

The modern world runs on silicon. Every advanced device, from your phone's processor to the chip in a self-driving car, relies on flawless, high-volume manufacturing. This is where the Product Development Engineer (PDE) steps in. They're the critical bridge. They are the ultimate product owner. They guide an integrated circuit (IC) from its first silicon sample through to profitable, mature mass production.

In FPV, if an SVA uses a gated clock, it could have false failures. Take the following SVA for example: // clk_gated does not toggle when block_busy == 0 assert property (@(posedge clk_gated) block…

In simulations, testbench may intentionally inject bubbles to a valid-ready interface, to check that the valid-ready interface can still functionally work. Such technique is called valid-ready slice staller, and it improves the coverage of valid-ready interface backpressure scenarios. One possible staller implementation is shown below: Valid-ready staller In the regular case, “stall_en” is low, and the staller is functionally transparent in the datapath; When enabling the staller, testbench will drive “stall_en” high, and the valid-ready interface is stalled. Testbench can randomly drive “stall_en” on a per cycle basis during simulation.

Coherence conflict happens when two cores compete for the read & write access for the cache line. False sharing, in particular, is a special type of coherence conflict, where two cores read and write different data that happen to reside in the same cache line. The coherence traffic incurred by coherence conflict / false sharing hurts performance when a core is waiting for coherence permissions for data access, and increases the load on the interconnection network / fabric.

A coherent DMA operation that reads memory should get the most recent version of data, even if the data resides in a cache in state M or O. Similarly, a coherent DMA operation that writes memory must invalidate stale copies in all caches. Though it is straightforward to handle coherent DMA by adding a coherent cache to the DMA controller, it it not desirable for a couple of reasons:

We assumed using write-back caches in cache coherence protocols. It is possible to use write-through caches as well. Advantages of using write-through caches: A significantly simpler two-state coherence protocol (Valid and Invalid). Stores write through the Last Level Cache (LLC) / memory, and invalidate all valid copies in other caches An L1 cache eviction requires no action besides changing the L1 state to Invalid, since LLC / memory always hold up-to-date data…

In the previous post, we discussed about handling non-atomic requests in directory based MSI protocol by stalls. In cache controller transient states such as “IS-D”, “IM-A” and “SM-A”, we could allow forwarded request messages to make progress without stalling, at the expense of adding more transient states. For example, when a cache controller has a line in State “IS-D” and receives an Inv message, it processes the request and changes the line’ state to “IS-D-I”, indicating the cache controller should change the line state to I after the “GetS” transaction completes.

A blog post covering tips and tricks that have proven effective for using Claude Code across various codebases, languages, and environments.

We love TPUs at Google, but GPUs are great too. This chapter takes a deep dive into the world of NVIDIA GPUs – how each chip works, how they’re networked together, and what that means for LLMs, especi...

Just like snooping based protocols, directory based cache coherence protocol has to handle non-atomic requests in real world implementations. We start from the a directory based MSI base model, and discuss one solution on non-atomic requests handling. Base Model In directory based MSI protocol, there are 3 message types: Request messages, including GetS, GetM, PutM and PutS Forwarded request messages, including Fwd-GetS, Fwd-GetM, Inv (Invalidation), and Put-Ack…

In the previous post, we discussed non-zero delay from coherence requests to responses. However, coherence requests may also be non-atomic: a coherence request may not be instantly ordered when it is issued by a cache controller. For example, if there is a request queue between a cache controller and the system bus, coherence request atomicity is no longer guaranteed, and this is a fairly common implementation.

In a previous post, we discussed one possible array sort solution without comparators. There are more comparison-free array sorting implementations available. In paper “An Efficient O(N) Comparison…

In a previous post, we discussed hardware implementation for array sorting using comparators. However, it is also possible to sort arrays without comparators. Surajeet Ghosh, Shaon Dasgupta and San…

Implementing hardware based array sorting is frequently asked when interviewing with high frequency trading companies. There are quite a few software based sorting algorithms that hardware implemen…

In cache coherence protocol implementation, designers must properly handle non-atomic operations, since coherence transactions cannot complete instantly. We start from the well-known snooping based…

Yet Another Latch and Gotchas Paper by Don Mills This paper discusses several SystemVerilog coding topics that can lead to inadvertent design bugs, including casex / casez expressions and unique / …

As SoCs are getting more complex, power becomes just as important as functionality correctness or performance. This article, “Unified Methodology for Effective Correlation of SoC Power Estimation and Signoff" by Infineon Technologies, addresses the growing challenges in accurately estimating and correlating power in complex SoCs. This article is a good start to understand how the ASIC industry handles power concerns intelligently and early.

Google released its “Gemini Prompting Guide 101” a while ago. Though the majority of the examples in this guide use Google Workspace for illustration purposes, it still provides a general ideal of writing effective prompts for all LLMs. The guide Four first illustrates the 4 main areas for effective prompts: Persona, i.e., assign a role to LLM to encourage creativity…

To understand cache coherence, we have to take one step back and look at the memory model first. What is a Memory Model? Memory consistency model, or memory model, dictates the order in which memory reads and writes (or loads and stores) get applied to coherence shared memory systems. In the world of computer architecture, memory reads (or loads) permanently change processors’ …