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Semiconductor Engineering @semiengineering.bsky.social · 23h

New technical papers recently added to Semiconductor Engineering’s library
semiengineering.com/chip-industr...

#semiconductor

Reposted by Semiconductor Engineering

Semiconductor Engineering @semiengineering.bsky.social · 4d

Latest news in the chip industry: semiengineering.com/chip-industr...

#semiconductor

Chip Industry Week in Review

Geopolitical hijinks: export controls, rare earths, and blacklists; SEMICON West announcement blitz; Intel readies 18A; AMD-OpenAI 6 GW deal; new 300mm GaN program; fab spending and EDA reports; acqui...

semiengineering.com

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Semiconductor Engineering @semiengineering.bsky.social · 2d

SemiEngineering has over 500 Tech Talk videos to learn from.
www.youtube.com/user/Sperlin...
Hot topics included challenges involving chiplets/ heterogeneous integration, AI, data management, DRAM, manufacturing and test & much more. Let us know what other topics are of interest.

#semiconductor

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Semiconductor Engineering @semiengineering.bsky.social · 4d

Latest news in the chip industry: semiengineering.com/chip-industr...

#semiconductor

Chip Industry Week in Review

Geopolitical hijinks: export controls, rare earths, and blacklists; SEMICON West announcement blitz; Intel readies 18A; AMD-OpenAI 6 GW deal; new 300mm GaN program; fab spending and EDA reports; acqui...

semiengineering.com

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Semiconductor Engineering @semiengineering.bsky.social · 4d

Location verification is gaining traction as a way of strengthening supply chain oversight with minimal effort, fueled by tightening export controls & growing concerns about AI chip smuggling & counterfeiting
semiengineering.com/location-ver...

#locationverification #semiconductor #locationtracking

Location Verification Becomes Much Bigger Concern For Chips

Mature methods can show where a chip is shipped, and even restrict where it is being used.

semiengineering.com

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Semiconductor Engineering @semiengineering.bsky.social · 5d

How 3D-IC Will Change Chip Design:
Stacking dies will dramatically improve performance, but it’s still a work in progress.
Final in 3 part series with 5 experts
semiengineering.com/how-3d-ic-wi...

#3DIC #semiconductor #chiplets

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Semiconductor Engineering @semiengineering.bsky.social · 6d

Smarter Packaging: How AI is Reshaping Assembly and Materials Control
semiengineering.com/smarter-pack...

Smarter Packaging: How AI is Reshaping Assembly and Materials Control

From predictive maintenance to excursion monitoring, AI is redefining yield management in multi-die assembly.

semiengineering.com

Semiconductor Engineering @semiengineering.bsky.social · 7d

Startup Funding: Q3 2025:
The third quarter was dominated by massive rounds, with 75 companies raising $6 billion.
semiengineering.com/startup-fund...
#semiconductor #startups #AI #photonics #quantum #AIhardware

Startup Funding: Q3 2025

Blowout quarter for AI and quantum; 75 companies raise $6 billion.

semiengineering.com

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Semiconductor Engineering @semiengineering.bsky.social · 8d

Special Report: Glass Substrates Gain Momentum:
semiengineering.com/glass-substr...

#semiconductor #GlassSubstrates

Glass Substrates Gain Momentum

Benefits increase with package size, but not all the kinks have been worked out.

semiengineering.com

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Semiconductor Engineering @semiengineering.bsky.social · 10d

Latest news and reports in the chip industry semiengineering.com/chip-industr...
#semiconductor

Chip Industry Week in Review

OpenAI DRAM capacity deals in Korea; $4.4B IC equipment merger; Taiwan rebuffs US' 50-50 split offer; EU Chips Act revision; Meta buys RISC-V startup; foundry report; imec transition; NIST disses Deep...

semiengineering.com

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Semiconductor Engineering @semiengineering.bsky.social · 26d

The chip industry traditionally has relied on margins to help them mitigate timing problems, but an increasing array of factors are now influencing timing. Can static timing analysis evolve to address these problems?
semiengineering.com/the-demise-o...

#verification #EDA #semiconductor

The Demise Of Static Timing Verification?

Timing is increasingly dependent on vectors. Can static techniques continue to deliver the necessary results? Maybe.

semiengineering.com

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Semiconductor Engineering @semiengineering.bsky.social · 27d

6G is expected to bring data speeds that enable highly integrated and responsive technology in smartphones, homes, cities, and autonomous vehicles, but realizing that goal will require a lot more work.
semiengineering.com/new-antennas...
#6G

New Antennas And Advanced ICs Needed For 6G

Higher frequencies bring more complexity to every part of the network, from tiny antennas to powerful base station processors.

semiengineering.com

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Semiconductor Engineering @semiengineering.bsky.social · 28d

The complexity of connecting different layers to create high-fidelity models, what those layers need to include, and why standards are needed to maximize their benefits and simplify their creation. With David Fried, VP at Lam Research
youtu.be/2ulbbpB-1W4?...

#semiconductor #virtualtwins

Virtual Twins

YouTube video by Semiconductor Engineering

youtu.be

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Semiconductor Engineering @semiengineering.bsky.social · 29d

New technical papers recently added to Semiconductor Engineering’s library:
semiengineering.com/chip-industr...

#semiconductor #DRAM #SRAM #EDA #MRAM #cybersecurity

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Semiconductor Engineering @semiengineering.bsky.social · Sep 12

Latest news in the chip industry semiengineering.com/chip-industr...

#semiconductor

Chip Industry Week in Review

Chinese site licenses for chip equipment; HBM4; Natcast layoffs; ASML's big AI investment; AI data center risks; critical minerals; Intel's leadership changes; MLPerf results; DRAM drilldown; soft mat...

semiengineering.com

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Semiconductor Engineering @semiengineering.bsky.social · Sep 11

A growing number of AI processors are being designed around specific workloads rather than standardized benchmarks, optimizing performance and power efficiency, but often with enough flexibility to adapt to future changes. semiengineering.com/balancing-wo...

#processors #AIworkloads #GPU #NPU #CPU

Balancing Workloads In AI Processor Designs

Optimization and architecture definition are important, but there's a downside to too much customization.

semiengineering.com

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Semiconductor Engineering @semiengineering.bsky.social · Sep 10

Limitations of supervised FDC, which relies on previous faults, and why unsupervised FDC is necessary to reduce scrap and predict where failures will occur. This is the third part in a seven-part series on AI in manufacturing.
semiengineering.com/using-ai-for...

Using AI For Fault Detection And Classification In Manufacturing

Supervised vs. unsupervised FDC and its impact on yield.

semiengineering.com

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Semiconductor Engineering @semiengineering.bsky.social · Sep 8

Changes are coming as DRAM is called upon to store & retrieve more data faster. This Tech Talk looks at how DRAM works, the impact of cooling new solutions in denser configurations, & ongoing issues involving the security of data.

semiengineering.com/the-evolutio...
#DRAM #HBM #LPDDR #GDDR

The Evolution of DRAM

How and why this tried-and-true memory is changing.

semiengineering.com

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Semiconductor Engineering @semiengineering.bsky.social · Sep 6

Chip Industry Technical Paper Roundup:
New technical papers recently added to Semiconductor Engineering’s library
semiengineering.com/chip-industr...

#semiconductor

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Semiconductor Engineering @semiengineering.bsky.social · Sep 5

Eventful week in the chip industry semiengineering.com/chip-industr...

#semiconductor

Chip Industry Week in Review

Cadence's $3.1B buy; new chip design to tapeout program; PWC's in-depth IC market analysis; new packaging consortium; high-NA EUV; revenue reports; tough new security regulations; India's buildout; Ge...

semiengineering.com

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Semiconductor Engineering @semiengineering.bsky.social · Sep 4

Special Report: Governments & systems companies are changing the rules around semiconductor security, forcing chipmakers and their suppliers to comply with tough new regulations that require resiliency in hardware.
semiengineering.com/security-req...

#semiconductor #cybersecurity #hardwaresecurity

Security Requirements And Penalties Grow For Chipmakers

Cost of designing chips and IP will increase, and companies at fault for breaches will be liable for damages.

semiengineering.com

Semiconductor Engineering @semiengineering.bsky.social · Sep 3

Challenges In Stacking HBM:
What changes are needed to stack 24 layers of high-bandwidth memory.
semiengineering.com/challenges-i...

#HBM #hybridbonding #warpage #metrology #datacenter

Challenges In Stacking HBM

What changes are needed to stack 24 layers of high-bandwidth memory.

semiengineering.com

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Semiconductor Engineering @semiengineering.bsky.social · Sep 2

Designing chips and systems to withstand brute-force attacks by quantum computers.
youtu.be/sEa4E_Z7m38?...

Preparing For The Quantum Computing Age

YouTube video by Semiconductor Engineering

youtu.be

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Semiconductor Engineering @semiengineering.bsky.social · Sep 1

Part average testing, one of the mainstays of semiconductor test, is becoming much more challenging at advanced nodes and in multi-die assemblies.
semiengineering.com/advanced-par...

#semiconductor

Advanced Part Average Testing For Chips

Unique designs and multi-die assemblies are forcing innovations at the leading edge of testing.

semiengineering.com

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Semiconductor Engineering @semiengineering.bsky.social · Sep 1

2025 Critical Hardware Weaknesses (Hardware CWE Special Interest Group)
semiengineering.com/2025-critica...

2025 Critical Hardware Weaknesses (Hardware CWE Special Interest Group)

A new technical paper titled “2025 Most Important Hardware Weaknesses” was published by researchers at Hardware CWE Special Interest Group. Excerpt “The Most Important Hardware Weaknesses (MIHW) empow...

semiengineering.com

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