Artur Lojewski
Artur Lojewski
@artur-lojewski.bsky.social
Introducing Ricursive Intelligence, a frontier AI lab enabling a recursive self-improvement loop between AI and the chips that fuel it.

#chip_design #ai #eat_your_own_dog_food #ricursive

www.ricursive.com
Recursive Self-Improvement via AI for Chip Design & Chip Design for AI - Riculsive Intelligence
We develop frontier AI methods to reinvent chip development, collapsing traditional design timelines, closing the loop between AI and the hardware that fuels it, and enabling a Cambrian explosion of c...
www.ricursive.com
December 3, 2025 at 7:15 AM
Lean Together online conference: 19—23 Jan 2026:

Lean Together is an annual meeting for users, developers, and fans of the Lean programming language and theorem proverand its library Mathlib maintained by the Lean Community.

#LeanLang #LeanProver

leanprover-community.github.io/lt2026/
Home
A meeting all about Lean
leanprover-community.github.io
October 21, 2025 at 1:52 PM
The Lean FRO ‘Year 3’ (August 2025 - July 2026) Roadmap - released today:

lean-lang.org/fro/roadmap/...

#LeanLang #roadmap #high_performance_verification #proof_automation
Lean Programming Language
Lean is a theorem prover and programming language that enables correct, maintainable, and formally verified code.
lean-lang.org
August 5, 2025 at 4:51 PM
Reposted by Artur Lojewski
#FPGA #RISCV
2GRVI Phalanx at Hot Chips 31: The First Kilocore RISC-V RV64I with HBM2 High Bandwidth Memory
fpga.org/2019/08/19/2...
2GRVI Phalanx at Hot Chips 31 (2019): The First Kilocore RISC-V RV64I with High Bandwidth Memory
This week at Hot Chips 31 (2019) I am presenting a status update poster on the work-in-progress GRVI Phalanx Accelerator Kit: 2GRVI Phalanx: Towards Kilocore RISC-V FPGA Accelerators with HBM2 DRAM…
fpga.org
November 12, 2024 at 4:55 AM
Attended Leo de Moura’s talk about @leanprover at #CADE_30 in Stuttgart/Germany. Lot’s of stuff in the pipeline! And whether it’s #Agda or #lean_lang I want to learn more about dependent types, proofs and how to apply them in my daily work!

The slides: leodemoura.github.io/files/CADE25...
leodemoura.github.io
July 31, 2025 at 12:19 PM
Reposted by Artur Lojewski
#JFS2025: Wie kann ich Java schneller starten – und wann lohnt sich das?

Schneller starten, weniger Ressourcen verschwenden: Von einfachem Tuning bis zu GraalVM Native Image gibt es viele Wege, Java-Anwendungen auf Tempo zu bringen.

www.java-forum-stuttgart.de/vortraege/wi...
Wie kann ich Java schneller starten – und wann lohnt sich das? - Java Forum Stuttgart
So können Java-Anwendungen schneller starten – sortiert nach aufsteigendem Geschwindigkeits-Gewinn: Framework-Tuning, Class Data Sharing (CDS), Project Leyden/JEP 483 (ab Java 24), CRaC und GraalVM Na...
www.java-forum-stuttgart.de
June 1, 2025 at 10:49 AM
Reposted by Artur Lojewski
#FPGA “With “A3CZ135BB18AE7S,
Largest Agilex 3 FPGA with 135K logic elements”.

Seems like a fine, modern hobbyist platform.

$169 per www.terasic.com.tw/cgi-bin/page...
Coming soon: Atum A3 Nano - a powerful, compact dev kit for the Altera Agilex 3 FPGA. Created by Terasic 🪄
Atum A3 Nano is part of Altera Innovation Lab
www.crowdsupply.com/terasic/atum...
Atum A3 Nano
A powerful, compact dev kit for the Altera Agilex 3 FPGA
www.crowdsupply.com
May 15, 2025 at 9:52 PM
The famous ‚Die Hard‘ problem with GenAI-accelerated TLAi+ by Markus Kuppe (now with NVIDIA):

youtu.be/JX_kTGHoYT8

#tlaplus #executableSpecification
Die Hard with GenAI-accelerated TLAi+
YouTube video by TLA+ - The Temporal Logic of Actions
youtu.be
May 15, 2025 at 5:53 PM
Yay! My Inspur XC7K480T FPGA development Board acceleration Card YPCB-00338-1P1 arrived!

#FPGA #Kintex #RISCV #openXC7
May 15, 2025 at 5:43 PM
From Luca Benini

The letter for support of open chip fabrication access for EU students, AKA *Democratizing silicon* for EU promoted by @pulp_platform and many others has already more than 300 signatories. We can do better, though. Please sign if you agree open-source-chips.eu
#open_source #chips
April 14, 2025 at 6:04 PM
Sam Altman:

…. we have greatly improved memory in chatgpt--it can now reference all your past conversations!

this is a surprisingly great feature imo, and it points at something we are excited about: AI SYSTEMS THAT GET TO KNOW YOU OVER YOUR LIFE, and become extremely useful and personalized.

👀
April 10, 2025 at 5:57 PM
LLM-accelerated TLA+? A proposal from #MarkusKuppe to develop MCP integration for TLA+ tools…Let’s see if this will be implemented in the near future! 😎

github.com/tlaplus/founda…#TLAPlusu#MarkusKuppep#TemporalLogici#ModelCheckingn#LLML#FormalVerificationon
https://github.com/tlaplus/founda…
March 24, 2025 at 7:56 AM
The Joy of Hardware Manifesto 🚀

joyofhardware.com

…Our in-browser IDE will let you write, compile, and program hardware without ever leaving your browser.

#FPGA #Bluespec #Nix
The Joy of Hardware
joyofhardware.com
March 22, 2025 at 8:14 PM
Engineers@Work! Decisions made by engineers to keep Mars Ingenuity (the helicopter 🚁) running! Or, you should be able to patch your system anytime! 😎

youtu.be/20vUNgRdB4o

#JPL #Mars #Ingenuity #ProblemSolving
Why Did The Mars Helicopter Disappear?
YouTube video by Veritasium
youtu.be
March 22, 2025 at 7:00 PM
Attempto Controlled English (ACE) is knowledge representation, specification, and a query language. For experts who want to use formal notations and formal methods, but may not be familiar with them.

#software_specifiation #ontology #proof_assistants

attempto.ifi.uzh.ch/site/
attempto.ifi.uzh.ch
March 20, 2025 at 8:20 AM
End-to-end vendor-neutral formal verification solution for RISC-V

youtu.be/V8n_-zz8SG0

#riscv #formalVerification #formalISA
Scenario Coverage In Formal Verification
YouTube video by Semiconductor Engineering
youtu.be
March 9, 2025 at 11:37 AM
Visualizing WiFi signals in a really cool way:

youtu.be/sXwDrcd1t-E

#ESP32 #wifi #visualize
This ESP32 Antenna Array Can See WiFi
YouTube video by Jeija
youtu.be
February 17, 2025 at 10:05 PM
#RISC-V Composable Extensions: The Extension Logic Interface *Workshop* with #RoCC, #CV_X_IF, #SCAIE_V and #CXU_LI presented as RISC-V extensions:

youtu.be/YtdVpkCIXtE
RISC V Technical Session | Extension Logic Interface Workshop
YouTube video by RISC-V International
youtu.be
February 14, 2025 at 3:39 PM
PULP Platform: Frank's slides presented yesterday at the First TAICHIP Winter School in Frankfurt an der Oder are now online. Find "PULP and AI Acceleration" here: pulp-platform.org/docs/taichip...

#AI #Acceleration #EnergyChallange
pulp-platform.org
February 12, 2025 at 3:48 PM
The Call For Papers (CFP) for the Java Forum Stuttgart 2025 started:
java-forum-stuttgart.de/cfp-anmeldung/

#Java #Kotlin #AI #JavaForumStuttgart
February 10, 2025 at 8:59 PM
DeepSeek is a Game Changer for AI - Computerphile: youtu.be/gY4Z-9QlZ64
DeepSeek is a Game Changer for AI - Computerphile
YouTube video by Computerphile
youtu.be
January 29, 2025 at 9:41 PM
Reposted by Artur Lojewski
☕️ We’re running LATTE again: our ASPLOS workshop about languages/compilers/tools/whatever for hardware design.

Submissions are just little 2-pagers, due on January 31. Plenty of time to throw something together! capra.cs.cornell.edu/latte25/
LATTE ’25
capra.cs.cornell.edu
January 9, 2025 at 5:15 PM