ASD/aspie, single (ace/demi), Gen Y. Currently lives in OK.
I have created a custom ISA, with emulator, Verilog implementation, and C compiler, here:
github.com/cr88192/bgbt...
Runs a custom ISA but now also can run RV64 (in userland), mostly targeting FPGA but aiming for OK performance. Mostly experimenting with ISA design.
github.com/cr88192/bgbt...
Have recently gone and implemented a small interpreter for a simplified JavaScript like language in roughly 2.7 kLOC of C. In this case, the interpreter was written in a way to try to limit line counts...
github.com/cr88192/bgbt...
Have recently gone and implemented a small interpreter for a simplified JavaScript like language in roughly 2.7 kLOC of C. In this case, the interpreter was written in a way to try to limit line counts...
Say:
Minimal (only enforce that it is valid UTF-8);
Partial: Normalize to either canonical UTF-8 or M-UTF-8;
More: Deal with combining characters and so on;
...
Say:
Minimal (only enforce that it is valid UTF-8);
Partial: Normalize to either canonical UTF-8 or M-UTF-8;
More: Deal with combining characters and so on;
...
I am left going back and forth on something:
Where I had put my RV64 jumbo prefix encoding conflicts with an older dropped "ADDIWU" instruction, and I am debating whether it is better to leave it where it is, or move the prefix elsewhere (probably into the same block as JALR).
I am left going back and forth on something:
Where I had put my RV64 jumbo prefix encoding conflicts with an older dropped "ADDIWU" instruction, and I am debating whether it is better to leave it where it is, or move the prefix elsewhere (probably into the same block as JALR).
I have created a custom ISA, with emulator, Verilog implementation, and C compiler, here:
github.com/cr88192/bgbt...
Runs a custom ISA but now also can run RV64 (in userland), mostly targeting FPGA but aiming for OK performance. Mostly experimenting with ISA design.
I have created a custom ISA, with emulator, Verilog implementation, and C compiler, here:
github.com/cr88192/bgbt...
Runs a custom ISA but now also can run RV64 (in userland), mostly targeting FPGA but aiming for OK performance. Mostly experimenting with ISA design.