Cyo
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cyothevile.bsky.social
Cyo
@cyothevile.bsky.social
Progressive
Idk if i would use that term, but I am capturing screen data into FPGA's SDRAM and scaling an image output.
January 27, 2026 at 9:43 PM
At this time I can serialize audio into the video stream. Sometimes tomorrow Ill get controller working and might dig around for capture card.
January 27, 2026 at 4:22 AM
After finding audio board and fixing backwards clock buffer (this broke a PCM and a buffer), and fixing FMT0 and FMT1 resistors to pullups, I got digital audio into the FPGA. Then I had to make an async fifo that was 48 wide for my PCM words.
Again, this took several hours for me to realize this.
January 27, 2026 at 4:22 AM
So I re-implemented the hsync vsync de generation organically in the softcore but still generate coordinates externally. The hdmi softcore was broken for hours when it was supposed to carry valid audio.
January 27, 2026 at 4:22 AM
2/2

I will order new board in a few weeks that is better with EMI and SI and shorten bridge FFC. Ill also begin designing the other subcarrier boards for other handhelds. If theres anything you want me to support let me know in comments please. Ill go buy one of them and study it.
January 1, 2026 at 3:54 PM