@marswise.bsky.social
🧠 How it works:
1️⃣ UARTLite core inside FPGA (AXI IP)
2️⃣ Connected to XDMA (PCIe) interface
3️⃣ On Linux side: custom TTY driver exposes /dev/ttyULx
4️⃣ Or use mmap: Python script → physical BAR registers
5️⃣ GPS SIM68 module talks over UART → logs into Linux!
✅ Works with any AXI IP (not just UART)
1️⃣ UARTLite core inside FPGA (AXI IP)
2️⃣ Connected to XDMA (PCIe) interface
3️⃣ On Linux side: custom TTY driver exposes /dev/ttyULx
4️⃣ Or use mmap: Python script → physical BAR registers
5️⃣ GPS SIM68 module talks over UART → logs into Linux!
✅ Works with any AXI IP (not just UART)
May 21, 2025 at 12:51 PM
🧠 How it works:
1️⃣ UARTLite core inside FPGA (AXI IP)
2️⃣ Connected to XDMA (PCIe) interface
3️⃣ On Linux side: custom TTY driver exposes /dev/ttyULx
4️⃣ Or use mmap: Python script → physical BAR registers
5️⃣ GPS SIM68 module talks over UART → logs into Linux!
✅ Works with any AXI IP (not just UART)
1️⃣ UARTLite core inside FPGA (AXI IP)
2️⃣ Connected to XDMA (PCIe) interface
3️⃣ On Linux side: custom TTY driver exposes /dev/ttyULx
4️⃣ Or use mmap: Python script → physical BAR registers
5️⃣ GPS SIM68 module talks over UART → logs into Linux!
✅ Works with any AXI IP (not just UART)