Longhorn
@never-released.mastodon.social.ap.brid.gy
Kernel/hypervisor engineer, Amazon EC2.
[bridged from https://mastodon.social/@never_released on the fediverse by https://fed.brid.gy/ ]
[bridged from https://mastodon.social/@never_released on the fediverse by https://fed.brid.gy/ ]
huh Xqci RISC-V extensions by Qualcomm for microcontrollers: https://github.com/quic/riscv-unified-db/releases/tag/Xqci-0.13.0
![The Xqci extension includes a set of instructions that improve RISC-V code density and performance
in microontrollers. It fills several gaps:
Long immediates
This extension provides wide-immediate versions of loads, stores, branches, jumps, and several
arithmetic operations.
Addressing modes
New indexed addressing modes are added for load and store instructions.
Load/store multiple
Xqci adds instructions that load multiple sequential values from memory into multiple registers.
Analogous instructions for stores are also included.
Branch immediate instructions
The base RISC-V ISA provides conditional branches that compare two register values. Xqci adds
conditional branch instructions that compare an immediate value to a register value, reducing a
common code sequence into a single instruction.
Conditional instructions
Xqci includes a variety of conditional select instructions that pick one of two operand values based on
the result of a condition and conditional move instructions that either move a value or retain a value in
a destination register based on the result of a condition. Conditional select and conditional move
instructions help reduce code size and avoid branches in common code sequences.
Extra bit manipulation instructions
Xqci expands upon the standard B extension by adding instructions for bit insertion/extraction, bit
set/clear, sign and zero extension, and bit counting instructions.
Fast interrupt instructions
[...]](https://cdn.bsky.app/img/feed_thumbnail/plain/did:plc:4c6mk7xhclk6sgkph24kkotb/bafkreihxpjh5fsskgic2l3puzbkn6d3qqkn3xwnkrmpxubtfgntfojflk4@jpeg)
December 24, 2025 at 6:05 PM
huh Xqci RISC-V extensions by Qualcomm for microcontrollers: https://github.com/quic/riscv-unified-db/releases/tag/Xqci-0.13.0
Not a Processing Unit
December 23, 2025 at 5:43 PM
Not a Processing Unit
isn't it funny that a Core Ultra 9 Processor 275HX + a 5070 Ti Laptop doesn't meet the specs to be a Copilot+ PC? lmao
December 23, 2025 at 1:12 PM
isn't it funny that a Core Ultra 9 Processor 275HX + a 5070 Ti Laptop doesn't meet the specs to be a Copilot+ PC? lmao
This blog post shocked me: https://elisa.tech/ambassadors/2025/12/10/schrodingers-test-the-dev-mem-case/
> safety
> /dev/mem
> adding an arbitrary constraint of not being able to set aside some memory
come on. just what. just taking a peek at the "enabling Linux for safety applications" […]
> safety
> /dev/mem
> adding an arbitrary constraint of not being able to set aside some memory
come on. just what. just taking a peek at the "enabling Linux for safety applications" […]
Original post on mastodon.social
mastodon.social
December 23, 2025 at 11:39 AM
This blog post shocked me: https://elisa.tech/ambassadors/2025/12/10/schrodingers-test-the-dev-mem-case/
> safety
> /dev/mem
> adding an arbitrary constraint of not being able to set aside some memory
come on. just what. just taking a peek at the "enabling Linux for safety applications" […]
> safety
> /dev/mem
> adding an arbitrary constraint of not being able to set aside some memory
come on. just what. just taking a peek at the "enabling Linux for safety applications" […]
sometimes the customer isn't always right tbh :/
imo very poor excuses here overall
imo very poor excuses here overall
December 23, 2025 at 11:34 AM
sometimes the customer isn't always right tbh :/
imo very poor excuses here overall
imo very poor excuses here overall
Some really oddball Linux ideas:
> Achieving ASIL B Qualified Linux
while minimizing expectations
from upstream kernel
from https://lpc.events/event/19/contributions/2132/attachments/1905/4076/LPC2025%20-%20Igor%20Stoppa.pdf […]
[Original post on mastodon.social]
> Achieving ASIL B Qualified Linux
while minimizing expectations
from upstream kernel
from https://lpc.events/event/19/contributions/2132/attachments/1905/4076/LPC2025%20-%20Igor%20Stoppa.pdf […]
[Original post on mastodon.social]
December 23, 2025 at 11:20 AM
Some really oddball Linux ideas:
> Achieving ASIL B Qualified Linux
while minimizing expectations
from upstream kernel
from https://lpc.events/event/19/contributions/2132/attachments/1905/4076/LPC2025%20-%20Igor%20Stoppa.pdf […]
[Original post on mastodon.social]
> Achieving ASIL B Qualified Linux
while minimizing expectations
from upstream kernel
from https://lpc.events/event/19/contributions/2132/attachments/1905/4076/LPC2025%20-%20Igor%20Stoppa.pdf […]
[Original post on mastodon.social]
looks like the CUDA dynamic parallelism rework (CDP2, mandatory on Hopper onwards) is changed just enough to not actually _need_ dynamic kernel dispatch prior to exit.
but can be implemented on top of indirect command buffers unlike the old one
but can be implemented on top of indirect command buffers unlike the old one
December 22, 2025 at 8:09 PM
looks like the CUDA dynamic parallelism rework (CDP2, mandatory on Hopper onwards) is changed just enough to not actually _need_ dynamic kernel dispatch prior to exit.
but can be implemented on top of indirect command buffers unlike the old one
but can be implemented on top of indirect command buffers unlike the old one
Apple gets a $115m fine from Italy over App Tracking Transparency
https://arstechnica.com/tech-policy/2025/12/apple-hit-with-115m-for-extremely-burdensome-app-store-privacy-policy/
https://arstechnica.com/tech-policy/2025/12/apple-hit-with-115m-for-extremely-burdensome-app-store-privacy-policy/
arstechnica.com
December 22, 2025 at 4:53 PM
Apple gets a $115m fine from Italy over App Tracking Transparency
https://arstechnica.com/tech-policy/2025/12/apple-hit-with-115m-for-extremely-burdensome-app-store-privacy-policy/
https://arstechnica.com/tech-policy/2025/12/apple-hit-with-115m-for-extremely-burdensome-app-store-privacy-policy/
ah the reason why Epic Games has to give out free games is that because their launcher is an atrocious product
December 22, 2025 at 9:13 AM
ah the reason why Epic Games has to give out free games is that because their launcher is an atrocious product
Replacing Helvetica with Arial across the board
December 21, 2025 at 7:10 PM
Replacing Helvetica with Arial across the board
wow the Epic Games launcher is atrocious and powers on the dGPU (???)
like wtf
like wtf
December 21, 2025 at 6:40 PM
wow the Epic Games launcher is atrocious and powers on the dGPU (???)
like wtf
like wtf
ok Arm but nobody outside of Arm will ever do this
> An Armv8-A implementation can be called an AArchv8-A implementation and an Armv9-A implementation can be called an AArchv9-A implementation.
> An Armv8-A implementation can be called an AArchv8-A implementation and an Armv9-A implementation can be called an AArchv9-A implementation.
December 21, 2025 at 10:43 AM
ok Arm but nobody outside of Arm will ever do this
> An Armv8-A implementation can be called an AArchv8-A implementation and an Armv9-A implementation can be called an AArchv9-A implementation.
> An Armv8-A implementation can be called an AArchv8-A implementation and an Armv9-A implementation can be called an AArchv9-A implementation.
so this 5070 Ti laptop only takes 100W over USB-C PD
and runs in a quite throttled mode over that.
To run properly it needs that giant 330W brick
and runs in a quite throttled mode over that.
To run properly it needs that giant 330W brick
December 21, 2025 at 6:46 AM
so this 5070 Ti laptop only takes 100W over USB-C PD
and runs in a quite throttled mode over that.
To run properly it needs that giant 330W brick
and runs in a quite throttled mode over that.
To run properly it needs that giant 330W brick
damn 5070 Ti laptop GPU throttles so much on a random gaming laptop when on battery
perf absolutely a _lot_ worse than when plugged (using ootb settings)
perf absolutely a _lot_ worse than when plugged (using ootb settings)
December 20, 2025 at 6:09 PM
damn 5070 Ti laptop GPU throttles so much on a random gaming laptop when on battery
perf absolutely a _lot_ worse than when plugged (using ootb settings)
perf absolutely a _lot_ worse than when plugged (using ootb settings)
GB10 has ASTC...
Quite a bit odd that all the Tegras from NVIDIA have ASTC but the dGPUs don't
https://vulkan.gpuinfo.org/displayreport.php?id=44645#device
Quite a bit odd that all the Tegras from NVIDIA have ASTC but the dGPUs don't
https://vulkan.gpuinfo.org/displayreport.php?id=44645#device
December 19, 2025 at 12:08 PM
GB10 has ASTC...
Quite a bit odd that all the Tegras from NVIDIA have ASTC but the dGPUs don't
https://vulkan.gpuinfo.org/displayreport.php?id=44645#device
Quite a bit odd that all the Tegras from NVIDIA have ASTC but the dGPUs don't
https://vulkan.gpuinfo.org/displayreport.php?id=44645#device
The NVIDIA Jetson Christmas ad this year is a bit of an oddball :D
https://www.youtube.com/watch?v=RJ8Yhy1OdYI
https://www.youtube.com/watch?v=RJ8Yhy1OdYI
December 16, 2025 at 5:53 AM
The NVIDIA Jetson Christmas ad this year is a bit of an oddball :D
https://www.youtube.com/watch?v=RJ8Yhy1OdYI
https://www.youtube.com/watch?v=RJ8Yhy1OdYI
RISC OS ARMv7 compatibility primer
Details the incompatible changes across AArch32 over the years and how it's possible despite those to have the same binary running across all of them
https://www.riscosopen.org/wiki/documentation/show/ARMv7%20compatibility%20primer
Details the incompatible changes across AArch32 over the years and how it's possible despite those to have the same binary running across all of them
https://www.riscosopen.org/wiki/documentation/show/ARMv7%20compatibility%20primer
RISC OS Open:
ARMv7 compatibility primer in Library
www.riscosopen.org
December 15, 2025 at 11:02 PM
RISC OS ARMv7 compatibility primer
Details the incompatible changes across AArch32 over the years and how it's possible despite those to have the same binary running across all of them
https://www.riscosopen.org/wiki/documentation/show/ARMv7%20compatibility%20primer
Details the incompatible changes across AArch32 over the years and how it's possible despite those to have the same binary running across all of them
https://www.riscosopen.org/wiki/documentation/show/ARMv7%20compatibility%20primer
spirv2clc: https://github.com/kpet/spirv2clc
An OpenCL SPIR-V to OpenCL C translator for recalcitrant OpenCL drivers to still be able to run SPIR-V binaries.
An OpenCL SPIR-V to OpenCL C translator for recalcitrant OpenCL drivers to still be able to run SPIR-V binaries.
GitHub - kpet/spirv2clc: Experimental OpenCL SPIR-V to OpenCL C translator
Experimental OpenCL SPIR-V to OpenCL C translator. Contribute to kpet/spirv2clc development by creating an account on GitHub.
github.com
December 15, 2025 at 2:08 PM
spirv2clc: https://github.com/kpet/spirv2clc
An OpenCL SPIR-V to OpenCL C translator for recalcitrant OpenCL drivers to still be able to run SPIR-V binaries.
An OpenCL SPIR-V to OpenCL C translator for recalcitrant OpenCL drivers to still be able to run SPIR-V binaries.
GPUs are fun
December 15, 2025 at 5:20 AM
GPUs are fun
clpeak, with clvk on KosmicKrisp
December 15, 2025 at 12:27 AM
clpeak, with clvk on KosmicKrisp
clinical, synthetic hugs
provided by AI bot
provided by AI bot
December 14, 2025 at 7:13 PM
clinical, synthetic hugs
provided by AI bot
provided by AI bot
not in shape for CCC this year but maybe the next one
December 13, 2025 at 6:56 AM
not in shape for CCC this year but maybe the next one
:-/
U.S. Government asks for social media profiles to be marked as public for H-1B, H-4, F, M and J NIVs
U.S. Government asks for social media profiles to be marked as public for H-1B, H-4, F, M and J NIVs
December 12, 2025 at 10:21 PM
:-/
U.S. Government asks for social media profiles to be marked as public for H-1B, H-4, F, M and J NIVs
U.S. Government asks for social media profiles to be marked as public for H-1B, H-4, F, M and J NIVs
wonder if it'd make sense to publish x86 nested virt for qemu on macOS in a tree somewhere
at this point it's way too late to be merged and most likely not worth reviewer time :/
at this point it's way too late to be merged and most likely not worth reviewer time :/
December 12, 2025 at 7:34 PM
wonder if it'd make sense to publish x86 nested virt for qemu on macOS in a tree somewhere
at this point it's way too late to be merged and most likely not worth reviewer time :/
at this point it's way too late to be merged and most likely not worth reviewer time :/
a Metal question: is there any advantage to using a private heap instead of shared on a (arm64) Mac?
MLX uses a shared one all the time
MLX uses a shared one all the time
December 12, 2025 at 5:49 PM
a Metal question: is there any advantage to using a private heap instead of shared on a (arm64) Mac?
MLX uses a shared one all the time
MLX uses a shared one all the time