### A Note From Our CEO As we head into the final quarter of the year, the progress across the RISC-V ecosystem is undeniable: RISC-V is here, ready, and exceeding expectations. In a few weeks, the global community will come together at RISC-V Summit North America 2025 in Santa Clara. Our keynote speakers will highlight RISC-V’s accelerating adoption and growth: Google will show how AI-driven automation is streamlining software portability, creating a “paved road” that accelerates RISC-V adoption; the SHD Group will unveil new analysis showing RISC-V surpassing 25% silicon market penetration, exceeding 20B units by 2031, and driving growth through Edge AI adoption; Microchip will demonstrate how RISC-V’s openness and adaptability are enabling secure, mission-ready platforms for the most demanding environments; the Ethereum Foundation will explore innovative use of RISC-V in blockchain and a growing role in zero-knowledge proof systems; and AWS will describe how designing processors in the Cloud through advanced emulation is democratizing access, accelerating innovation cycles and reducing costs. These speakers represent just a glimpse of the expertise and innovation you’ll experience. Be there in Santa Clara to engage with the full lineup and help shape the future of RISC-V. Alongside these keynote insights, I’m particularly excited about our hands-on developer workshops, where attendees can learn directly from experts on topics ranging from processor design to software optimization and then apply the lessons learnt through hands-on labs. This is where knowledge is transferred, skills are sharpened, and the next wave of innovation begins. It’s been great to see RISC-V take the stage not just in North America, but around the world. At the RISC-V Automotive Conference in Munich, we highlighted RISC-V’s role in the future of the software-defined vehicle and the growing commitment of the automotive ecosystem, while the RISC-V Summit in China brought forward incredible momentum and adoption stories across Asia. These events reinforce what we see every day: a strong, diverse, and growing global community shaping the future of computing together. The path ahead is clear. With collaboration, openness, and determination, we are transforming the way the world thinks about hardware and software. I hope to see you in Santa Clara this October as we continue building the foundation for the next era of innovation. – Andrea Gallo, CEO, RISC-V International ### **Upcoming Events** **Event** | **Date** | **Location** | **Details** ---|---|---|--- RISC-V Andes Con | October 14 | Munich, Germany | Learn More. RISC-V Summit North America | October 21-23 | Santa Clara, California | Register Today! LF Europe Roadshow | October 29 | Ghent, Belgium | Learn More. embedded world North America | November 4-6 | Anaheim, California | Learn More. All of the upcoming RISC-V events can be found here! ### RISC-V In The News Some of the most popular news stories from the last 3 months. Explore More News ### RISC-V Content The most popular content from the last 3 months, from RISC-V International and community members. Discover More Blogs Do you have news or blogs we can amplify? The blog, In the News, and social media submission request form can be found on the RISC-V News & Blog page. ### Explore RISC-V by Industry ### **Stay Connected with RISC-V** Follow us on our social channels! Ecosystem news and updates are shared on our X and LinkedIn feeds.

### Project Snapshot Post-Quantum Cryptography (PQC) is a topic of increased interest in the past decade, both with regards to the cryptosystem definition and the hardware and software implementations to perform at optimum efficiency. We present our ongoing work on the implementation of RISC-V based accelerators for PQC algorithms, in particular the Classic McEliece Key Encapsulation Mechanism. Our system includes a PQC accelerator and an Open-HW Group CVA-6 core along with a PQC-specific instruction set. This presentation describes the architecture, performance estimates, and demonstration plans in the future. ### In Their Own Words ### Poster Preview ### Want to Dive Deeper? Read the full paper on the author’s site Continue Reading ### Meet the Authors ##### **Dr. Ambily Suresh** #### **Senior Scientist at Silicon Austria Labs, Graz in Austria** Dr. Ambily Suresh is a Senior Scientist at Silicon Austria Labs. After her bachelor’s in Electronics and Communications Engineering, she spent a few years as an ASIC Design Engineer and was involved in multiple tapeouts. She spent the next decade building instruments and technologies for space astronomy, while doing her PhD from the Indian Institute of Astrophysics at Bangalore and postdoctoral research at the University of Colorado at Boulder. At SAL, she focuses on digital design and ASIC implementation of RISC-V based accelerators. ##### **Dr. Manuel Freiberger** #### **Senior Scientist at Silicon Austria Labs, Graz in Austria** Manuel Freiberger is a senior scientist at Silicon Austria Labs with a PhD in Biomedical Engineering from Graz University of Technology. His early academic work focused on developing algorithms and reconstruction techniques for fluorescence optical tomography. After completing his doctorate, he spent several years in industry, where he contributed to the design and development of high-precision measurement instruments for particle sizing and nano-surface metrology. Currently, he is engaged in research and development projects at the intersection of digital design and artificial intelligence, with a focus on compiler-based tooling and hardware-aware algorithm development. ##### **Andrew Wilson** #### **Junior Scientist at Silicon Austria Labs, Graz in Austria** Andrew Wilson is a junior scientist at SAL. He obtained his Bachelors in Mechatronic Engineering at Ulster University after which he worked R&D at an ISTAR company before starting his masters at SAL in 2023. He is an Open Source and General Software/Engineering/Physics Enthusiast in my spare time among many other things. ##### **Dr. Diego Gigena-Ivanovich** #### **Scientist at Silicon Austria Labs, Graz in Austria** _Dr. Diego Gigena Ivanovich is a Scientist in the Embedded Artificial Intelligence group at Silicon Austria Labs in Linz, Austria. He holds a PhD from the National University of the South (UNS), Argentina, where he conducted his doctoral studies under the supervision of Prof. Pedro Julián. His research focuses on the design and ASIC implementation of custom hardware accelerators for machine learning applications within the RISC-V ecosystem. By combining low-power digital design techniques with ML algorithms, he aims to enable high-performance inference on resource-constrained edge devices._ ##### **Dr. Willibald Krenn** #### **Head of Research Division****at Silicon Austria Labs, Graz in Austria** Dr. Willibald Krenn is the Head of the Embedded Systems Research Division at Silicon Austria Labs. His research interest focuses on HW/SW co-design of dependable intelligent systems at Silicon Austria Labs (SAL). Before joining SAL, he led the Dependable Systems Engineering-team of the AIT Austrian Institute of Technology GmbH and was working as a compiler engineer in a FPGA-based high performance computing start-up in London. Willibald holds a PhD (“Self reasoning in resource constrained devices”) from Graz University of Technology and really enjoys being able to bring together his passion for AI and dependable systems in the context of RISC-V.

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RISC-V International’s new CEO Andrea Gallo sees the open ISA accelerating across verticals, from AI and automotive to data centers and supercomputing. Speaking with JPR, he highlighted Nvidia’s CUDA port,...

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### Project Snapshot Fault Injection Attacks (FIA) present considerable threats to the security and reliability of embedded systems. FIAs can compromise an embedded processor by altering its clock signal, power supply or by using electromagnetic pulses. This study focuses on analyzing the impact of FIA on the Physical Memory Protection (PMP) configuration flow within a CVA6 RISC-V core. We conducted fault injection campaigns on an FPGA implementation using an ARTY A7-100T board to characterize the resulting fault effects. To achieve this, we utilized clock glitches as the primary method of fault injection. Our experimental findings reveal that FIAs can induce various effects on PMP configuration registers. By categorizing these effects according to the injection parameters, we demonstrate that specific effects can be reliably achieved under varying injection conditions, often with a high probability of success for an attacker. ### In Their Own Words ### Poster Preview ### Want to Dive Deeper? Read the full paper on the author’s site Continue Reading ### Meet the Authors ##### **Kévin QUENEHERVE** #### **PHD Student in Electrical and Computer Engineering at****Université Bretagne Sud (UBS) – Lab-STICC (UMR CNRS 6285) in France** Kevin Queneherve is a PhD student in the ARCAD team of Lab-STICC laboratory (UMR CNRS 6285) at Université Bretagne Sud (UBS), Lorient, France. After obtaining a master’s degree in CyberSecurity of Embedded Systems in UBS, he completed an end-of-study internship within the ARCAD team on the performance and security analysis of the memory isolation mechanism of RISC-V cores for embedded systems. His current research work focuses on the study and design of an embedded processor robust against fault-injection attacks. ##### **Philippe TANGUY** #### **Associate professor in Electrical and Computer Engineering at****Université Bretagne Sud (UBS) – Lab-STICC (UMR CNRS 6285) in France** Philippe Tanguy is associate professor at Université de Bretagne Sud (UBS). He teaches at the Université de Bretagne Sud in the UFR SSI. He performs his research activities at Lab-STICC in the ARCAD team. He had a PhD in Electronics and digital communication at IETR. Currently, his research activities are dedicated to IoT system with a focus on the Cybersecurity issues. ##### **Rachid DAFALI** #### **Researcher Teacher** at **DGA MI in France** ##### **Vianney LAPÔTRE** #### **Associate professor in Electrical and Computer Engineering at****Université Bretagne Sud (UBS) – Lab-STICC (UMR CNRS 6285) in France** Vianney Lapôtre received his M.Sc and Ph.D in Electrical and Computer Engineering from the Université Bretagne Sud, France, in 2010 and 2013 respectively. In 2012, he spent six months as a visiting researcher at Ruhr University in Bochum, Germany. From 2013 to 2014, he was a Postdoctoral at LIRMM, Montpellier. In 2023, he was awarded my habilitation to direct research (HDR). He is currently associate professor at University Bretagne Sud, France. He is a member of the ARCAD team of the Lab-STICC laboratory. His research interests include hardware security, embedded processors and reconfigurable hardware architectures.

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