I also take macro photos of electronics
A DFF in front of the ECP5's FPGA SPI configuration port before a mix leading to FLASH and PSRAM. Enabling an initial jump through FLASH where the clock frequency is bumped and QSPI entered.
This now fixes an issue violating the PSRAM's tCE<8us requirement.
A DFF in front of the ECP5's FPGA SPI configuration port before a mix leading to FLASH and PSRAM. Enabling an initial jump through FLASH where the clock frequency is bumped and QSPI entered.
This now fixes an issue violating the PSRAM's tCE<8us requirement.
Voltages all look good
Voltages all look good