Here's a graphic of the situation, showing the overlay on the 738 BIOS, an empty byte that was gained by turning the JP into a JR. Below that the older 728 BIOS which still uses JP, and has the underlying routine shifted right by a byte. The overlay overwrites the underlying '1B' of the JP address.

It seems the overlay was made for the SVI-738, which uses a newer International #MSX ROM and they applied it to the SVI-728 without realizing the underlying ROM is incompatible!

Please consider supporting my research on Buy Me A Coffee so I can continue to find and fix such issues next year!

My first wishes:
-V9990 I/O level compatibility
-Sprite Linking with relative coordinates. There's a little known feature of MSX-BASIC for moving multi-layered sprites with 1 PUT SPRITE instruction. Doing this in hardware, adding relative coordinates, you could move and animate large objects easily.

まったくオリジナルと同じです！

Many a programmer writing an SCC detection algorithm has run into this behavior. So generally reads to the test register are avoided in detection methods, but one could devise a test that specifically detects IKASCC this way.

I wonder how other FPGA implementations fare.

On MSX with pull-ups, yes. Without pull-ups it may be anything 🎉

Sorry, it's channels 1, 2 and 3 afterall.

I'm not talking about the bus. Testing (on MSX) shows that reading the test register causes the wave data for (only!) channel 3 to start rotating. It appears this behavior can't be reached by writing any value to the test register, but writing 0 will make it behave normally again. Strange, right?

If you like Discord, you can join msx.center for lots more info, pictures and videos on these MSX developments.

The motherboard with R80 CPU uses another TangNano20K, this is still in the design phase. The V9968 VDP is basically feature complete but requires some more testing and bugfixing, but there will be a live demo this weekend at an MSX DEVCON in Tokyo. The plan is to release MSX2++ sometime in 2026.

Yes, MSX2++ is currently in development by @thara1129.bsky.social, the hardware is his design. Pictured below is the TangNano20K FPGA, that's used to implement the V9968 VDP, attached to a development board. The V9968 VDP is also mostly HRA!'s own vision, with some pointers by me 😊

forward path:
MSX1 (prototype)
MSX2 (intended specs w/ V9938 VDP)
MSX2+ (polished specs w/ V9958 VDP)
MSXturboR (innovate w/ dual Z80 & R800 CPU)
MSX2++ (ultimate 8-bit w/ R80 CPU & V9968 VDP)
MSXturboR+ (ultimate 16-bit w/ R900 CPU & V9978 VDP)
MSX3 (next-gen 32-bit w/ R1800 CPU & V9988 VDP)

(3/3)

ask me to create the MSX2++ firmware OS (based on my MoSX project), and HRA!'s hardware design expertise, it became possible to depart from the MSXturboR's innovative but complex dual CPU architecture and settle on a single R80 CPU with several operating modes. This ensures compatibility and a (2/3)

Which do you prefer? Both designs have their merits.

omg

I have everything except the box. The seller (back in the 90s) felt that sending the box was not necessary and just stuffed the contents in an envelope. 😢

It's been incorporated in HRA!'s CHKVDP utility