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InstLatX64
@instlatx64.bsky.social
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x86/x64, SIMD, #AVX512, "Aha!" moments. I have been writing code since 1986. Budapest, Europe https://instlatx64.github.io/InstLatx64/
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#Intel #VPMM is back in the 7th edition of "Intel® TDX Module Base Architecture Specification (What Changed)".
Probably just a documentation bug.
cdrdv2-public.intel.com/867556/intel...
#AMD & #Intel unified future instructions:
#FRED #AVX10 #ChkTag #ACE (=ACE (Advanced Matrix Extensions for Matrix Multiplication): www.amd.com/en/blogs/202...
It is a top-secret place :)
#AMD refreshed the "Revision Guide for AMD Family 1Ah Models 00h-0Fh Processors" 58251 to v1.10 pdf
(#Turin #Zen5 C1 CPUID B00F21 #EPYC)
docs.amd.com/v/u/en-US/58...
#AMD refreshed the "Revision Guide for AMD Family 1Ah Models 10h-1Fh Processors" 58730 to v1.30 pdf
(#TurinD #Zen5c B0 CPUID B10F10 #EPYC)
docs.amd.com/v/u/en-US/58...
#Intel #Pantherlake #CougarCove/#Darkmont differences over the 18A process, so far:
- ISA additions (CGC/DMR)
- Better frontend/branch prediction (CGC/DMR)
- P21 bounded insts (CLMUL, GF2MUL?) doubled throughput (DMT)
- 19 -> 17 clks L2 latency (SMT->DMT)
#VisualStudio2026 18.0.0 Insider implements the so far missing #AVX10_VNNI_INT instructions too.
#DiamondRapids #NovaLake
#Intel released the 59th edition of the ISA Extensions Reference with some #PantherCove, #CoyoteCove and #ArcticWolf microarchitecture details:
#DiamondRapids #NovaLake #WildcatLake

Download:
cdrdv2-public.intel.com/865891/31943...

#AMX_TRANSPOSE removed
The redesigned #AMD Technical Information Portal:
docs.amd.com
An example of how virtualization distorts CPUID. For this reason, they should not be included in my collection, similar to Engineering Samples.
#AMD #Zen5 #Threadripper