InstLatX64
@instlatx64.bsky.social
x86/x64, SIMD, #AVX512, "Aha!" moments.
I have been writing code since 1986.
Budapest, Europe
https://instlatx64.github.io/InstLatx64/
I have been writing code since 1986.
Budapest, Europe
https://instlatx64.github.io/InstLatx64/
I think there should be a third CCD type, e.g. a 24-core one.
November 24, 2025 at 3:13 PM
I think there should be a third CCD type, e.g. a 24-core one.
I think the "more AI pipelines" on #AMD #Zen6 means that ADD/SUB/MIN/MAX/CVT uops of "New AI Datatype"(=FP16) can go into FP23 ports also, against the FP01-bounded #AVX512_VNNI / #AVX_VNNI uops.
November 20, 2025 at 12:11 PM
I think the "more AI pipelines" on #AMD #Zen6 means that ADD/SUB/MIN/MAX/CVT uops of "New AI Datatype"(=FP16) can go into FP23 ports also, against the FP01-bounded #AVX512_VNNI / #AVX_VNNI uops.
cc: @fclc.bsky.social
What can means DFMA here?
What can means DFMA here?
November 11, 2025 at 1:54 PM
cc: @fclc.bsky.social
What can means DFMA here?
What can means DFMA here?
..and the favorite
VPTERNLOG[B,W] - how useful would be this! e.g. byte granularity, single-uop (mask)?0:(c?a:b)
Source:
www.sandpile.org/x86/opc_3.htm
3/3
VPTERNLOG[B,W] - how useful would be this! e.g. byte granularity, single-uop (mask)?0:(c?a:b)
Source:
www.sandpile.org/x86/opc_3.htm
3/3
sandpile.org -- x86 architecture -- 3 byte opcodes
www.sandpile.org
November 11, 2025 at 1:44 PM
..and the favorite
VPTERNLOG[B,W] - how useful would be this! e.g. byte granularity, single-uop (mask)?0:(c?a:b)
Source:
www.sandpile.org/x86/opc_3.htm
3/3
VPTERNLOG[B,W] - how useful would be this! e.g. byte granularity, single-uop (mask)?0:(c?a:b)
Source:
www.sandpile.org/x86/opc_3.htm
3/3
#AVX512BITALG2 completes these useful instructions:
VPLZCNT[B,W] - the missing byte & word LZCNT
VPTZCNT[B,W,D,Q] - Analogous to LZCNT[B,W,D,Q]
VPADD[,U]S[D,Q] - saturated signed / unsigned addition for dword / qword (but why there isn't VPSUB[,U]S[D,Q]?)
2/3
VPLZCNT[B,W] - the missing byte & word LZCNT
VPTZCNT[B,W,D,Q] - Analogous to LZCNT[B,W,D,Q]
VPADD[,U]S[D,Q] - saturated signed / unsigned addition for dword / qword (but why there isn't VPSUB[,U]S[D,Q]?)
2/3
November 11, 2025 at 1:44 PM
#AVX512BITALG2 completes these useful instructions:
VPLZCNT[B,W] - the missing byte & word LZCNT
VPTZCNT[B,W,D,Q] - Analogous to LZCNT[B,W,D,Q]
VPADD[,U]S[D,Q] - saturated signed / unsigned addition for dword / qword (but why there isn't VPSUB[,U]S[D,Q]?)
2/3
VPLZCNT[B,W] - the missing byte & word LZCNT
VPTZCNT[B,W,D,Q] - Analogous to LZCNT[B,W,D,Q]
VPADD[,U]S[D,Q] - saturated signed / unsigned addition for dword / qword (but why there isn't VPSUB[,U]S[D,Q]?)
2/3